Who this programme is for
Graduates who want to work on proving that a design is correct before it is manufactured. Verification is the largest hiring pool in the semiconductor industry and the most code-heavy — if you enjoy programming as much as hardware, this is your track.
What you will be able to do
- Write a complete UVM testbench from scratch, not from a template you do not understand
- Build constrained-random stimulus and know when directed tests are the better tool
- Write functional coverage and assertions that actually catch bugs
- Close coverage methodically and report verification status credibly
- Debug a failing simulation from waveform to root cause
Syllabus
Module 1 — Verilog and digital design refresher
RTL coding styles, simulation semantics, race conditions, and the design constructs you will be verifying.
Module 2 — SystemVerilog for verification
Data types, classes and inheritance, randomisation and constraints, interfaces and clocking blocks, mailboxes and semaphores, and the object-oriented thinking the methodology depends on.
Module 3 — Building a testbench by hand
Before touching UVM you build a layered testbench yourself — driver, monitor, scoreboard, generator — so that every UVM class you meet later maps onto something you have already written.
Module 4 — UVM
Component hierarchy and phases, sequences and sequencers, the factory and overrides, configuration database, TLM ports, virtual sequences, and the register abstraction layer.
Module 5 — Coverage and assertions
Functional coverage modelling, covergroups and cross coverage, SystemVerilog Assertions, and building a verification plan that links features to coverage points.
Module 6 — Protocol verification
AMBA protocols — APB, AHB and AXI — with a verification environment built for one of them as a graded exercise.
Module 7 — Capstone
Verify a non-trivial DUT end to end: verification plan, UVM environment, coverage closure and a written sign-off report.