Who this programme is for
Graduates who want to write the hardware itself — turning a specification into synthesisable RTL that meets timing, area and power budgets. Strong digital fundamentals are essential.
What you will be able to do
- Write clean, synthesisable Verilog and SystemVerilog that a tool maps the way you intended
- Design FSMs, pipelines, arbiters, FIFOs and memory interfaces from a spec
- Handle clock domain crossing correctly instead of hoping for the best
- Read synthesis and timing reports and change your RTL in response
- Implement a standard bus protocol interface from the specification document
Syllabus
Module 1 — Digital design fundamentals
Combinational and sequential logic, timing basics, setup and hold at the register level, metastability, and number representation.
Module 2 — Verilog and SystemVerilog for design
Synthesisable subset, blocking versus non-blocking assignment, inference of latches and flops, parameterisation, generate constructs, and coding styles that survive review.
Module 3 — Design building blocks
Counters, shift registers, FSM styles, synchronous and asynchronous FIFOs, arbiters, round-robin schedulers, and memory interfacing.
Module 4 — Clock domain crossing
Two-flop synchronisers, handshake and pulse synchronisers, gray-coded FIFO pointers, reset synchronisation, and CDC verification.
Module 5 — Synthesis and timing awareness
Constraints, critical path analysis, pipelining and retiming, resource sharing, and low-power RTL techniques including clock gating.
Module 6 — Protocols and capstone
Implement an AMBA APB or AHB interface from the specification, integrate it into a small subsystem, verify it, and close synthesis timing.