Track: VLSI
-
RTL Design with Verilog & SystemVerilog
Turn specifications into clean synthesisable RTL that meets timing, handles clock domain crossing and survives review.
-
VLSI Design Verification (UVM)
Build UVM testbenches from first principles, write coverage that finds real bugs, and close verification methodically.
-
VLSI Physical Design
Take a synthesised netlist through floorplanning, placement, CTS, routing and timing closure to a sign-off-clean layout.