These are the questions that come up again and again in physical design and verification interviews for freshers. What follows is not a list of answers to memorise — interviewers can tell instantly — but the reasoning each question is probing for, so you can answer from understanding.
Timing fundamentals
1. What is setup time and hold time?
Setup is how long data must be stable before the clock edge; hold is how long it must remain stable after. The follow-up is always “why do both exist?” — because a flip-flop is built from latches and internal gates that need time to resolve a value. Answer with the physical reason, not the definition.
2. Which violation is more serious, setup or hold?
Hold. A setup violation can often be rescued by slowing the clock; a hold violation is independent of clock frequency, so if it survives to silicon the chip is broken at any speed. This question separates people who understand the checks from people who memorised them.
3. What is metastability and how do you handle it?
When setup or hold is violated the output can hover between logic levels for an unbounded time. You cannot eliminate it across asynchronous boundaries, only make it arbitrarily improbable — the two-flop synchroniser gives the first flop a full clock period to resolve. Expect a follow-up on MTBF.
4. What is clock skew, and is it always bad?
Skew is the difference in clock arrival time between two flops. Positive skew toward the capture flop helps setup and hurts hold. Useful skew exploits this deliberately. Saying “skew is bad” marks you as a textbook reader.
5. Setup and hold equations
Be able to write them without hesitating:
Setup: T_launch + T_cq + T_logic_max + T_setup ≤ T_period + T_capture - T_uncertainty
Hold: T_launch + T_cq + T_logic_min ≥ T_capture + T_holdPhysical design flow
6. Walk me through the flow from RTL to GDSII
Synthesis, floorplanning, power planning, placement, CTS, routing, physical verification, sign-off. Name the inputs and the exit criteria for each stage rather than listing the words.
7. What is congestion and how do you fix it?
Demand for routing resources exceeding supply in a region. Fixes: reduce utilisation, spread cells, adjust macro placement and halos, use blockages, upsize the standard cell rows or add metal layers. Mention the tension with timing — the fixes that relieve congestion often spread a critical path out.
8. Why is CTS done after placement and before routing?
You need real cell locations to know the clock sink positions, and you want the clock tree routed with priority before signal routing consumes the tracks.
9. What is an antenna violation?
During fabrication, a long metal segment connected to a gate accumulates charge that can damage the thin oxide. Fixes: layer jumping with vias, or inserting a diode. Note that it is a manufacturing effect, not an electrical one in the finished chip.
10. IR drop — what causes it and what do you do?
Resistive voltage loss in the power grid under switching current. Lower supply means slower cells, so it becomes a timing problem. Fixes: strengthen the grid, add straps, insert decoupling capacitors, spread high-activity cells.
Digital design
11. Blocking versus non-blocking assignment
Blocking for combinational logic, non-blocking for sequential. Be ready to explain the simulation race that results from getting it backwards, and why it may still synthesise to something that works.
12. How do you cross clock domains?
Two-flop synchroniser for single bits. For multi-bit data, never synchronise each bit independently — use a gray-coded asynchronous FIFO or a handshake, because independent bits will land on different cycles.
13. Why gray code in asynchronous FIFOs?
Only one bit changes per increment, so a pointer sampled mid-transition is either the old or the new value — never a garbage intermediate.
14. Latch versus flip-flop
Level sensitive versus edge sensitive. Expect a follow-up on accidental latch inference from an incomplete if or case in combinational logic.
15. How do you reduce dynamic power?
Clock gating, operand isolation, reducing switching activity, voltage and frequency scaling. Know the P = αCV²f relationship and which term each technique attacks.
Verification
16. Why constrained random rather than directed tests?
Random stimulus reaches corner cases a human would not think to write. Directed tests still matter for specific known scenarios. The honest answer is that you need both, guided by coverage.
17. Code coverage versus functional coverage
Code coverage says which lines ran; functional coverage says which features were exercised. 100% code coverage with weak functional coverage is a comfortable illusion.
18. What does the UVM factory give you?
Runtime substitution of one class for another without editing the environment — the basis of testbench reuse.
The two questions that decide the interview
19. Tell me about your project
This carries more weight than any technical question, because it is unscripted and they can drill as deep as they like. Know what you did, why you chose it, what went wrong, and what you would do differently. A modest project you understand completely beats an impressive one you followed along with.
20. Do you have questions for us?
Always yes. Ask what the team is working on, what a first project would look like, what tools they run. “No questions” reads as no interest.
How to prepare
Say your answers out loud. Fluency on paper is not fluency under pressure, and the gap between the two is where good candidates lose offers. If you can explain setup and hold to someone from another branch and have them understand it, you are ready for that question.
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