Who this programme is for
ECE, EEE and allied graduates who want to work on the back end of chip design — the stage where a synthesised netlist becomes a manufacturable layout that meets timing, power and area targets. You should be comfortable with digital electronics and CMOS fundamentals before you start.
What you will be able to do
- Take a netlist through floorplanning, placement, CTS and routing to a clean layout
- Read a static timing analysis report and explain every number in it
- Diagnose and fix setup, hold, transition and capacitance violations
- Run physical verification and interpret DRC and LVS failures
- Explain your flow decisions to an interviewer without hand-waving
Syllabus
Module 1 — Foundations
CMOS fundamentals revisited for back-end work: standard cells, library characterisation, Liberty timing models, the ASIC design flow end to end, and where physical design sits within it.
Module 2 — Floorplanning and power planning
Die and core area estimation, utilisation targets, macro placement strategy, pin placement, blockages, power grid construction, IR drop and electromigration basics.
Module 3 — Placement
Global and detailed placement, congestion analysis and relief, scan chain reordering, placement-stage timing optimisation and the trade-offs between congestion and timing.
Module 4 — Clock tree synthesis
Clock skew and latency, CTS constraints and exceptions, buffer and inverter trees, useful skew, clock gating, and post-CTS timing closure.
Module 5 — Routing
Global, track and detailed routing, NDRs, shielding, crosstalk and signal integrity, antenna violations and their fixes, and metal fill.
Module 6 — Static timing analysis
Setup and hold checks, timing paths and exceptions, SDC constraints, multi-corner multi-mode analysis, OCV and derating, and systematic timing ECO strategy. This module carries the most interview weight and gets the most lab time.
Module 7 — Physical verification and sign-off
DRC, LVS and ERC, sign-off checklists, power analysis, and preparing a block for hand-off.
Module 8 — Capstone
Take a block from netlist to sign-off on your own, document every decision, and defend it in a review that runs like a real interview.
Tools and scripting
Industry-standard place-and-route and timing tools, with Linux and Tcl scripting throughout — back-end work is scripted work, so you will write your own automation rather than clicking through a GUI.